When a semiconductor device is manufactured, generally, a semiconductor wafer is repeatedly subjected to various processes such as a film deposition process and a pattern etching process, so as to manufacture a desired device. In view of recent demand for higher integration degree and further miniaturization of a semiconductor device, a line width thereof and/or a hole diameter thereof have been made smaller and smaller. In accordance with such smaller dimensions, electric resistance has to be made smaller. Thus, there is a tendency to use copper as a wiring material and/or an embedded material, because copper has smaller electric resistivity and is inexpensive (see, JP-A-2000-77365). When copper is used as a wiring material and/or an embedded material, a tantalum metal (Ta) film or a tantalum nitride (TaN) film is used as a barrier layer in consideration of adhesive properties between the copper material and a lower layer thereof.
In order to form such a barrier layer, a tantalum nitride film (hereinafter also referred to as “TaN film”) or a tantalum film (hereinafter also referred to as “Ta film”) is formed at first as a base layer on a surface of a wafer in a plasma sputtering apparatus. Then, in the same plasma sputtering apparatus, an additional tantalum film is formed (when the base layer is a Ta film, the film deposition conditions are varied). Thus, a barrier layer is formed. Thereafter, a thin seed film made of a copper film is formed on a surface of the barrier layer, and the entire wafer surface is plated with copper to fill a recess.
A lower wiring layer and an upper wiring layer, which are stacked with an insulation film therebetween, are electrically connected in the following manner. Firstly, the insulation layer is formed on the lower wiring layer. Then, a communication hole, such as a via hole and a through hole, is formed in the insulation layer to expose the lower wiring layer at a bottom part of the communication hole. Thereafter, the communication hole is filled with a material of the upper wiring layer, and the upper wiring layer is deposited at the same time. As described above, since the line width is to be narrowed and the hole diameter is to be reduced in accordance with the demand for miniaturization, it is necessary to take measures to lower electric resistance in the connecting structure between the upper and lower wiring layers. As an example of the measures, the through hole is formed such that the bottom part thereof is “embedded” to a predetermined thickness of the lower wiring layer, so that contact resistance between an embedded material to be “embedded” in the bottom part of the through hole and the lower wiring layer is reduced. Such a structure is referred to as a so-called “punch-through structure”. A method of forming this structure is referred to as a so-called “punch-through process”.
An example of the punch-through process is described with reference to FIGS. 12A to 12C and FIGS. 13A to 13E. FIGS. 12A to 12C show a communication hole formed in a semiconductor wafer which is not yet filled. FIG. 12A is a plan view of the semiconductor wafer whose communication hole is not yet filled. FIG. 12B is a sectional view of the semiconductor wafer taken along the line A-A shown in FIG. 12A. FIG. 12C is a perspective view of the semiconductor wafer shown in FIG. 12A. FIGS. 13A to 13E are views for explaining a filling step of the communication hole.
As shown in FIGS. 12A to 12C, the semiconductor wafer W is formed of a silicon substrate, for example. A lower wiring layer 102 made of copper, and an insulation layer 104 formed of a silicon oxide film are stacked on a surface of the silicon substrate in this order. A recess 105 is formed in a surface of the insulation layer 104. The recess 105 has a wiring groove of a predetermined width, i.e., a trench 106, for forming an upper wiring layer. In a bottom part of the trench 106, there is partially formed a communication hole 108 which passes through the insulation layer 104 to reach the lower wiring layer 102. The communication hole 108 will function as a via hole or a through hole. A diameter L1 of the communication hole 108 is significantly small, e.g., between about 60 nm and about 200 nm. A width L2 of the trench 106 is, e.g., between about 60 nm and about 1000 nm.
In order that the communication hole 108 and the trench 106 are filled, as shown in FIG. 13A, a barrier layer 110 of a metal film is formed at first by plasma sputtering, for example, on an entire surface of the wafer W including a surface in the trench 106 and a surface in the communication hole 108, for improving adhesive properties between the wafer surface and a base layer and for preventing diffusion and migration of copper into the insulation layer 104. As the barrier layer 110, there is mainly employed a two-layered structure including a tantalum nitride film (TaN film) and a tantalum film (Ta film), or a two-layered structure including two tantalum films which have been deposited under different (varied) deposition conditions.
Then, as shown in FIG. 13B, by plasma etching using an Ar gas as an inert gas, a part of the barrier layer 110 formed on the bottom part of the communication hole 108 is scraped. Further, the lower wiring layer 102 as a base of the barrier layer 110 is etched so that a scraped recess 112 of a predetermined depth is formed.
Then, as shown in FIG. 13C, a very thin electro-plating seed film 114 is formed on the entire surface including the inner surfaces of the scraped recess 112, of the communication hole 108, and of the trench 106, by sputtering, for example. A copper (Cu) film is used as the seed film 114 because copper plating is performed in the subsequent step, for example.
Then, as shown in FIG. 13D, electro-plating is performed from the seed film 114 as a starting point, so that the scraped recess 112, the communication hole 108, and the trench 106 are respectively filled with the material of an upper wiring layer 116. As described above, copper is used, for example, as the material of the upper wiring layer 116.
Thereafter, as shown in FIG. 13E, the upper unnecessary metal material is removed by grinding or the like, whereby there is formed the upper wiring layer 116 which is electrically connected to the lower wiring layer 102.
Due to the provision of the communication hole 108 such as a through hole or a via hole in the bottom part of the trench 106, the recess 105 has a two-stepped cross-section. Such a shape of the recess 105 is referred to as a so-called “Dual Damascen structure”.
At the plasma etching step shown in FIG. 13B, particles of the barrier layer, which are scattered by etching at a corner indicated by a point P1, for example, are scattered within a predetermined angle range in a certain direction with a specific directivity. This feature does not pose a serious problem when the line width and the groove width are relatively wide. However, since the groove width is as small as about 100 nm, as described above, there is a possibility that the particles, scattered in the certain direction by this feature may adhere to an opposed wall surface to form a deposition projection 118 on the opposed wall surface. When the deposition projection 118 is formed, at the following plasma sputtering step shown in FIG. 13C, the deposition projection 118 generates a shadow, which invites a so-called shadowing phenomenon, because the sputtered particles have a high directivity. Namely, the seed film 114 does not adhere to a shadow part 120 by the deposition projection 118. When there remains a part on which the seed film 114 does not adhere, a void 122 is undesirably generated at that part, as shown in FIG. 13D.
FIGS. 14A and 14B are views for comparing recesses 105 (trenches 106) whose widths L2 are different from each other. In fact, various recesses 5 having different widths L2 may be formed in the surface of the semiconductor wafer W, as shown in FIGS. 14A and 14B. In that case, as shown in FIGS. 14A and 14B, angles θ1 and θ2, which are viewed upward from the bottom parts of the communication holes 108, may differ from each other (θ1<θ2), when aspect ratios of the trenches 106 are different, even if aspect ratios of the communication holes 108 are the same (the diameters L1 thereof are the same). Thus, thicknesses H1 and H2 of the barrier layers 110, which are deposited on the bottom parts of the communication holes 108 as the lowermost layers in the recesses 105, may differ from each other. Because of the difference in the thicknesses H1 and H2 of the barrier layers 110, depths of the scraped recesses 112 formed by scraping the barrier layers 110 may differ from each other.